1. Technical Field
The invention relates generally to integrated circuit (IC) chips, and more particularly, to a capacitor having electrodes extend to different depths to reduce parasitic capacitance.
2. Background Art
Vertical natural (VN) capacitors are used in integrated circuit (IC) chips. FIG. 1 shows one illustrative conventional capacitor 8 in which inter-digitated cathodes 10 and anodes 12 are generated in layers of an IC chip. Quality of capacitor 8 is defined mainly by resistance of inter-digitated electrodes 10, 12, and parasitic capacitance coupling to an underlying substrate 14. Quality can be improved by reducing resistance and parasitic capacitance. Parasitic capacitance to underlying substrate 14 or underneath wiring 16 of capacitor 8 is mainly due to the fringe capacitance of inter-digitated electrodes 10, 12 and the parasitic capacitance of a bottom level 18 of capacitor 8. One approach to reduce the parasitic capacitance to underlying substrate 14 is to move bottom level 18 of capacitor 8 away from underlying substrate 14 to a higher back-end-of-line (BEOL) layer. Unfortunately, this approach also greatly reduces the main capacitance of capacitor 8.